2nd IEEE International Workshop on
Automated Test Equipment: Vision ATE 2020
Santa Clara Convention Center, Santa Clara, California, USA
October 30-31, 2008
Held in conjunction with TestWeek (International Test Conference 2008)

ITC Test Week
2008 Workshop
Workshop Details
 Call For Papers (pdf doc)
Workshop Registration
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General Chair
E. Volkerink, Verigy
General Co-Chair
Y. Zorian, Virage Logic
Program Chair
S. Davidson, Sun Microsystems
Program Co-Chair
M. Kondrat, Cascade Microtech
Panel Chair
A. Khoche, Verigy
Finance Co-Chair
R. Chandramouli, ARM
Publicity Chair
A. Gold, Advantest
Marketing Chair
F.-F. Ferhani, Broadcom
Program Committee
R. Barth, Numonyx
P. Burlison, Inovys
K.-Y. Cho, NVIDIA
C. J. Clark, Intellitech
A. Evans, Broadcom
W. Fister, Micron
G. Fleeman, Advantest
B. Gage, Teradyne
M. Hafed, DFT Microsystems
B. Price, NXP
R. Kapur, Synopsys
D. Keezer, GeorgiaTech
R. Lesnikoski, Sun Microsystems
J. Moreira, Verigy
P. Muhmenthaler, Infineon
M. Roos, Roos Instruments
J. Rivoir, Verigy
N. Touba, University of Texas
C.W. Wu, Tsing Hua University



2008 Schedule

2008 Keynote Speaker:
Octavio Martinez




ATEVision Interview in T&M World


2007 Workshop Pictures (100 Attendees)

Scope: The workshop will examine where the ATE industry is heading in the near-term as well as in the long-term. Integrated circuits get denser, larger, and faster and more heterogeneous. As the number of dies in a single package increases, so does the test quality target. Certain dies require Known-Good-Die (KGD) quality levels, whereas more complex failure modes already challenge our yield learning curves.

These issues, when added to increasing Cost-Of-Test (COT), Time-To-Volume (TTV), and Time-To-Market (TTM) pressures, driven by today's high-volume market applications, pose significant challenges to the ATE industry. To meet those challenges the industry needs to innovate in areas such as test methodologies, interconnection technologies, architectures, and Design-For-Testability (DFT) and Design-For-Manufacturability (DFM) technologies.

The goal of this workshop is to create an informal forum to discuss those innovations relevant to ATE developers and users. We are looking for solutions to the issues of 2012 and beyond, not those of 2009. Are our roadmaps addressing future test challenges? Are we investing our research dollars in the right areas? Do we have the right business models in place to succeed in the future? Join the discussion!

Representative topics include, but are not limited to:
  • Design for Testability (BIST, BISR)
  • Test methods for future defects
  • Adaptive Design Techniques
  • ATE/EDA Link
  • High-speed IO ATE
  • Low-cost ATE
  • RF ATE
  • ATE for Statistical Test

Corporate Supporters
Advantest
ARM
Cascade MicroTech
Optimal Test
Mentor Graphics
Pintail Technologies
Roos Instruments
Demiconductor Test Consortium
Syntest
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  • Cadence
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  • Syntest
  • Teradyne
  • Verigy
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