2nd IEEE International Workshop on Automated Test Equipment: Vision ATE 2020
Santa Clara Convention Center, Santa Clara, California, USA October 25-26, 2007 Held in conjunction with TestWeek (International Test Conference 2008) Downloadable Program Here! Thursday, October 30, 2008 Session 1 - ATE Vision Opening 4:00pm - 4:05pm Opening Remarks  Erik Volkerink, General Chair 4:05pm - 4:10pm Opening Remarks  Scott Davidson Program Chair 4:10pm - 5:00pm Keynote Address Octavio Martinez, Director of Test Engineering, Qualcomm 5:00pm - 6:30pm Panel: Creating Sustainable Growth: Trick or Treat!!! Chair: Rick Nelson, Test & Measurement World Panelists:         Brad Robbins, Teradyne         Deb Ahlgren, Verigy         Gary Fleeman, Advantest         Dan Glotter, OptimalTest Organizer: Ajay Khoche, Verigy 7:00pm - 8:30pm Reception, Santa Clara Convention Center, Ballroom E & F Friday, October 31, 2008 7:00am - 8:00am Breakfast Session 2 – ATE Architectures of the Future Chair: Dave Keezer, Georgia Tech 8:00am - 8:30am 2.1 Driving Industry Collaboration to the Next Level Paul Roddy, Advantest 8:30am - 9:00am 2.2 Functional ATE Architecture for the Next 10 Years   Ronald Lesnikoski, Sun Microsystems 9:00am - 9:30am 2.3 The Configurable Modular Tester (CMT)   Mark Roos, Roos Instruments 9:30am - 10:00am 2.4 A Path to Efficiency   Kris Hublitz and Andy Evans, Broadcomm 10:00am - 10:30am Break  Session 3 –New Concepts in Testing Chair: 10:30am - 11:00am 3.1 Future of Testing = Adapt Evolve Win   John Bearden and Gil Balog, OptimalTest 11:00am - 11:30am 3.2 At-Speed Loopback Testing: Strategies and Techniques   Jose Moreira, Joerg Walter Mohr and Roger Nettles, Verigy 11:30am - 12:00pm 3.3 To Wire or Not to Wire?-That is the Question!   Chih-Tsun Huang, National Tsing-Hua University   12:00pm - 1:00pm Lunch Session 4 – The Future of Test Chair: Mike Kondrat, Cascade Microtech 1:00pm - 1:30pm 4.1 Forecast: Discontinuities   Eric Strid, Cascade Microtech 1:30pm - 2:00pm 4.2 Test and DFT Challenges for the "More than Moore" Era   Prasad Matnri, Sun Microsystems ; 2:00pm - 2:30pm 4.3 What Will a Typical IC Test Program Look Like in 2015?   Phil Burlison, Verigy 2:30pm - 3:00pm Break  Session 5 – ATE & EDA Chair: 3:00pm - 3:30pm 5.1 Integrating ATE Test In The Design Flow - Closing The CAE / ATE Gap   Kirit Khichadia, Simutest 3:30pm - 4:00pm 5.2 Consideration of ATE Simulation in EDA Environment   Yuhai Ma, Advantest 4:00pm - 4:30pm 5.3 An Automatic Functional Stress Pattern Generation Technique Suitable for SoC Reliability Characterization   D. Appello *, P. Bernardi ***, M. Bruno ***, R. Cagliesi **, M. Giancarlini **, M. Grosso ***, E. Sanchez *** and M. Sonza Reorda ***, * ST Microelectronics, ** ELES Semiconductor Equipment, Todi, ***Politecnico Torino 4:30pm Raffle for Attendees &Open Mike & Adjourn